Implementation of 8x8 Dadda Multiplier Using Approximate Compression for Image Enhancement
نویسنده
چکیده
Inexact (Approximate) computing is an attractive paradigm for digital processing. Inexact computing is particularly interesting for computer arithmetic designs. This project deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different features of compression, such that imprecision in computation can make up for circuit-based figures of merit of a design. Two different schemes for utilizing the proposed approximate compressors are proposed and analysed for a Dadda multiplier. Extensive simulation results are provided and hardware implementation of the Dadda multiplier using approximate compression is carried out with the help of a Field Programmable Gate Array (FPGA).
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